This application claims the benefit of Korean Patent Application No. 2002-21680, filed Apr. 19, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
The present invention relates to the field of delay line circuits such as Delay Locked Loops (DLLs), and more particularly, to delay line control circuits and methods for DLLs.
In integrated circuit chip Dynamic Random Access Memories (DRAMs), the skew of a clock signal in the integrated circuit chip may affect the operation of the DRAM. A DLL circuit may be used as a compensator for skew of an internal clock signal in a DRAM and/or other integrated circuit chips. The structure and operation of DLLs is well known to those having skill in the art and are described, for example, in U.S. Pat. Nos. 6,459,314; 6,452,432; 6,434,083; 6,388,485; 6,366,148; 6,285,225; 6,222,894; 6,101,137; 5,901,190; and 5,880,612, all of which are assigned to the assignee of the present application.
Unfortunately, a DLL can cause an increase in current consumption in an integrated circuit. Accordingly, in a precharge mode before a DRAM is activated, or in a power-down mode, the DLL is disabled so as to reduce or minimize current consumption of the DLL. In this case, the DLL latches locked phase information in a register, and thus this locked state is maintained.
When the DRAM exits from the precharge mode or power-down mode, all unit delay cells of the DLL selected from locked phase information latched in the register are simultaneously turned on. In this process, a large amount of current may instantaneously flow from an internal supply to a ground voltage of the DLL, and therefore the internal supply voltage of the DLL may become unstable. After all of the selected unit delay cells are simultaneously turned on, the clock signal sequentially passes the selected unit delay cells and a time delay occurs.
FIG. 1 is a block diagram of a conventional delay line control circuit with a delay locked loop (DLL). FIG. 2 is a logic diagram of control signals used to control unit delay cells shown in FIG. 1.
Referring to FIG. 1, the conventional delay line control circuit 100 with a DLL includes first through sixth unit delay cells DC1, DC2, . . . , and DC6 and first through sixth registers REG1, REG2, . . . , and REG6, each of which receives an inverted signal BSTBY of a standby signal, and first through sixth shift turn-on signals ONSFT1, ONSFT2, . . . , and ONSFT6 and generates first through sixth control signals CTRL1, CTRL2, . . . , and CTRL6, respectively, used to control the first through sixth unit delay cells DC1, DC2, . . . , and DC6. It will be understood that even though only six of the unit delay cells DC1, DC2, . . . , and DC6 and/or six of the registers REG1, REG2, . . . , and REG6 are shown in FIG. 1, a different number of unit delay cells and/or registers can be used.
Referring to FIG. 2, a control signal CTRL that is used to control unit delay cells DCs is generated in response to an inverted signal BSTBY of a standby signal and a shift turn-on signal ONSFT(ixe2x88x921) stored in a register REG before the DLL is locked. It is seen from FIG. 2 that the control signal CTRL is activated only if the inverted signal BSTBY of the standby signal and the shift turn-on signal ONSFT(ixe2x88x921) are activated.
The operation of the conventional delay line control circuit 100 with the DLL will be described with reference to FIGS. 1 and 2.
In a precharge mode or power-down mode, the standby signal STBY is at a high level and an inverted signal BSTBY of the standby signal STBY is at a low level. Thus, the first through sixth control signals CTRL1, CTRL2, . . . , and CTRL6 of the first through sixth registers REG1, REG2, . . . , and REG6 are generated at low levels. Hence, all of the first through sixth unit delay cells DC1, DC2, . . . , and DC6 are turned off. However, phase information of the first through sixth unit delay cells DC1, DC2, . . . , and DC6 before the DRAM enters the precharge mode or power-down mode are stored in the first through sixth registers REG1, REG2, . . . , and REG6. When the DRAM exits from the precharge mode or power-down mode, the standby signal STBY is at a low level, and the inverted signal BSTBY of the standby signal STBY is at a high level. Since the shift turn-on signal ONSFT(ixe2x88x921) stored in the first through sixth registers REG1, REG2, . . . , and REG6 is at a high level, the first through sixth control signals CTRL1, CTRL2, . . . , and CTRL6 are at high levels, and therefore the first through sixth unit delay cells DC1, DC2, . . . , and DC6 are activated.
Assuming the first through third unit delay cells DC1, DC2, and DC3 are activated before the DRAM enters the precharge mode or power-down mode in FIG. 1, if the DRAM exits from the precharge mode or power-down mode, the first through third control signals CTRL1, CTRL2, and CTRL3 generated by the first through third registers REG1, REG2, and REG3 are at high levels, and therefore the first through third unit delay cells DC1, DC2, and DC3 are simultaneously turned on. If the first through third unit delay cells DC1, DC2, and DC3 are selected, an internal clock signal INTCK is sequentially transferred to the first through third unit delay cells DC1, DC2, and DC3.
FIG. 3 illustrates an internal circuit of the unit delay cell shown in FIG. 1. Referring to FIG. 3, the unit delay cell includes resistors R connected to supply voltages VCC and first through tenth NMOS transistors MN1, MN2, . . . , MN9, and MN10.
In operation of the internal circuit, the fifth NMOS transistor MN5 and the tenth NMOS transistor MN10 are turned on in response to a high level of a bias signal VBIAS. If a unit delay cell turn-on signal DCON is applied at a high level, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the eighth NMOS transistor MN8, and the ninth NMOS transistor MN9 are turned on. If the internal clock signal INTCK is applied at a high level, the first NMOS transistor MN1 is turned on, the supply voltage VCC is applied to the sixth NMOS transistor MN6, and the high level of the supply voltage VCC is output as an output signal OUTCK. If the internal clock signal INTCK is at a high level, an inverted signal BINTCK of the internal clock signal INTCK is naturally at a low level, and thus the second NMOS transistor MN2 and the seventh NMOS transistor MN7 are turned off.
If the DRAM exits from the precharge mode or power-down mode and the first through third unit delay cells DC1, DC2, and DC3 are simultaneously turned on, the internal clock signal INTCK should pass through the previous first and second unit delay cells DC1 and DC2 so that the internal clock signal INTCK is transferred to the third unit delay cell DC3. Thus, a time delay occurs, and the first through third unit delay cells DC1, DC2, and DC3 are simultaneously turned on, and current consumption is instantaneously increased in the unit delay cells. Hence, the internal supply voltage of the DLL may be unstable. This can be seen from FIG. 3. If the internal supply voltage of the DLL is unstable, the delay time of the unit delay cells may vary. This may affect a data output time, and further may negatively affect jitter characteristics.
Delay line circuits and controlling methods according to some embodiments of the present invention include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding unit delay cell is connected to an input of a succeeding unit delay cell. At least two of the unit delay cells in the series are sequentially activated in response to an activation signal. The sequential activation may be performed by a control circuit that is connected to the series of unit delay cells.
In some embodiments, a respective one of the unit delay cells also includes a respective control input. The control circuit includes a series of control signal generators, a respective one of which includes first and second inputs and first and second outputs that are sequentially connected, such that a respective first output is connected to a respective control input, the first output of a preceding control signal generator is connected to the first input of a succeeding control signal generator, and the second input of a succeeding control generator is connected to the second output of a preceding control signal generator. The activation signal is connected to the first input of a first control signal generator in the series of control signal generators. Accordingly, some embodiments of the present invention can reduce or prevent the instantaneous flow of a large amount of current through the series of unit delay cells. Some embodiments may be used in a DRAM when the standby state of the DRAM is converted into an active state. Jitter thereby may be reduced or minimized.
Delay line circuits according to other embodiments of the invention include a delay line portion and a control portion. The delay line portion has first through N-th, where N is an integer, unit delay cells, at least some of which receive an output of the previous unit delay cell, delay the output for a predetermined amount of time and output a delayed value, wherein an internal clock signal is input to the first unit delay cell. The control portion is configured to generate first through N-th control signals used to activate and deactivate the first through N-th unit delay cells in response to a predetermined activation signal. The first through N-th unit delay cells are sequentially activated in response to the activation signal. The control portion includes first through N-th control signal generating portions, a respective one of which corresponds to a respective one of the first through N-th unit delay cells and that is configured to generate the first through N-th control signals in response to predetermined first through N-th input signals, and first through N-th shift turn-on signals.
In some embodiments, the first input signal is the activation signal, and the second through N-th input signals that are input to the second through N-th control signal generating portions are control signals generated by the previous first through N-th control signal generating portions.
In some embodiments, the first control signal generating portion is turned on or off in response to the first shift turn-on signal, and each of the second through N-th control signal generating portions is turned on or off in response to the second through N-th shift turn-on signals output from the previous first through N-th control signal generating portions.
In some embodiments, the first through N-th control signals are activated when the corresponding shift turn-on signals and the corresponding control signals are activated.
In other embodiments, the delay line circuit includes first through N-th delay portions. The first delay portion generates a first delay signal in which an internal clock signal is delayed for a predetermined amount of time, and a second shift tun-on signal in response to a predetermined first shift turn-on signal and a predetermined first input signal. The second delay portion generates a second delay signal in which the first delay signal is delayed for a predetermined amount of time, and a third shift turn-on signal in response to the second shift turn-on signal and a predetermined second input signal. The N-th delay portion generates an N-th delay signal in which an (Nxe2x88x921)-th, where N is an integer more than 3, delay signal is delayed for a predetermined amount of time, and an (N+1)-th shift turn-on signal in response to an N-th shift turn-on signal, and a predetermined N-th input signal. The first through N-th delay portions are sequentially activated.
In some embodiments, each of the first through N-th delay portions includes a control signal generating portion which generates a control signal used to activate and deactivate a unit delay cell in response to the corresponding input signal and the shift turn-on signal, and a unit delay cell which delays an input signal for a predetermined amount of time in response to the control signal and outputs the input signal as the delay signal. The first control signal generating portion of the first delay portion is turned on or off in response to the first shift turn-on signal, and each of the second through N-th control signal generating portions of the second through N-th delay portions is turned on or off in response to the first through N-th shift turn-on signals that are output from the previous first through N-th control signal generating portions. In some embodiments, the first through N-th control signals of the first through N-th delay portions are activated when the corresponding shift turn-on signals and the corresponding control signals are activated.
In some embodiments, in the first delay portion, the internal clock signal is input to the unit delay cell, and the first input signal is an operation activation signal indicating that the operation of a delay line circuit is activated. In each of the second through N-th delay portions, each of control signals generated by the control signal generating portion of the previous delay portion is received as the second through N-th input signals, and the delay signal generated in the unit delay cell of the previous delay portion is input to the unit delay cell. The first through N-th control signal generating portions comprise registers.
In delay line circuits and controlling methods according to embodiments of the present invention, unit delay cells are sequentially turned on in response to an activation signal, such as when a standby state of the DRAM is converted into an active state. Upon activation, instantaneous flowing of a large amount of current through the DLL can be reduced or prevented and jitter of the DLL can be reduced or minimized.